SiFive's BigSky Ships: The First Rackable RISC-V Server Runs Ubuntu, RHEL 10 — and CUDA

For the first time, a RISC-V server you can actually rack is in customers’ hands. SiFive introduced the BigSky SF-2U870 at an event coinciding with Hot Chips in Santa Clara on August 24, 2026, describing it as the world’s first enterprise-grade, rackable 2U RISC-V server. The platform is available today in limited quantities, with lead customers — hyperscalers, software vendors, and major SoC hardware companies — already running workloads on deployed systems, and SiFive says demand is outpacing supply.

Two things make this more than an IP vendor’s vanity hardware project. First, the software story: BigSky is fully compliant with the ratified RVA23 profile, boots Canonical Ubuntu 26.04 LTS and Red Hat RHEL 10 out of the box, and eliminates the custom porting work that has kept RISC-V out of enterprise fleets. Second, the AI story: CUDA is now running on the P870-D-powered platform, with BigSky serving as a head node orchestrating LLM workloads on NVIDIA GPUs — a capability never before demonstrated on RISC-V hardware.

The hardware: a dev platform that looks like a real server

The BigSky SF-2U870 is built explicitly for software porting, workload tuning, and validation testing rather than for winning SPEC benchmarks. The specifications:

• 32 SiFive P870-D cores operating at 2.0 GHz (SiFive’s 6-wide out-of-order performance core, scaling to 32 cores per cluster and up to 256 coherent cores over a CHI bridge in larger configurations)
• 256GB DDR5-5600 memory
• 4× PCIe Gen5 x16 (64 lanes) plus PCIe Gen3 x4
• 2× 7.68TB U.2 NVMe SSDs
• 10/25Gb OCP 3.0 NIC
• Standard 19-inch 2U rack form factor

SiFive published no performance data, power figures, or pricing with the launch — honest signals that this is a development vehicle, not a product aimed at displacing x86 sockets today. What it proves is compatibility and readiness: that the RISC-V server software stack exists, boots standard enterprise Linux, and can host real datacenter workloads.

Why RVA23 compliance is the whole ballgame

The gating factor for RISC-V in the datacenter has never been silicon — it’s been software fragmentation. The RVA23 profile, ratified by RISC-V International, defines a common instruction-set baseline (including Vector 1.0 and Vector Crypto extensions) that lets one binary run across vendor implementations interchangeably, much like the Armv9 server profiles did for Arm’s Neoverse generation.

At the Hot Chips tutorial on August 23, RISC-V International Chief Architect Krste Asanović said 2026 is the year RVA23 server-class silicon appears from multiple vendors, able to boot standard Linux distributions interchangeably, with the RISC-V server platform spec covering UEFI, ACPI, and IOMMU requirements already ratified.

The enterprise Linux commitment predates the hardware. Canonical’s Gordan Markuš described a full rebuild of roughly 30,000 packages on RVA23 for Ubuntu 25.10, promoted to the 26.04 LTS release in April 2026, with Debian package availability for RISC-V at roughly 95% of the most-deployed architectures. Red Hat’s RHEL 10 support extends the same commitment to the second enterprise distro that matters. One honest asterisk from Canonical’s own tutorial disclosure: emulation timeouts currently limit full-archive testing to roughly 3,000 packages, and native RISC-V build infrastructure is still under construction — availability is proven at 95%, but correctness at full parity is a 2026 deliverable that BigSky-class native hardware itself will help close.

CUDA on RISC-V: claiming the GPU head node

The most strategically loaded demo is CUDA. SiFive has been working with NVIDIA to port CUDA to SiFive-based RISC-V hardware and to integrate NVLink Fusion into future SiFive platforms — the follow-through on the partnership the two companies announced in January 2026.

The measure of progress came from NVIDIA’s Frans Sijstermans at the Hot Chips tutorial: a year ago, no RVA23 CPU existed that CUDA could be ported onto; at least three now sit in NVIDIA’s labs, and the requirements beyond the RVA23 profile and server platform specs total roughly two pages — principally PCIe coherency and peer-to-peer support. BigSky’s demo makes one of the three public.

Why does the head node matter? In agentic AI infrastructure, the CPU is being restored to the center: orchestration, tool calls, and KV-cache management all live on the host processor, while the GPUs do the tensor math. NVIDIA builds its own Vera CPU on a custom Arm core for exactly this duty. NVLink Fusion exists because some customers want that seat filled by silicon they control — and a hyperscaler that already licenses SiFive IP can now validate the CUDA path on merchant hardware before committing to a custom design. The toll for production NVLink Fusion duty remains NVIDIA’s coherent C2C interconnect, which SiFive describes as planned for future platforms rather than shipping in this one.

The Arm analogy — and where it breaks

Analysts read BigSky as a porting vehicle whose real product is time. Arm needed a decade of Neoverse iterations, Graviton proof points, and enterprise Linux parity before Axion and Cobalt-200 could displace x86 sockets at fleet scale. RISC-V server CPUs now sit roughly where Arm sat around 2018: profiles ratified, distros booting, first silicon reaching customers.

The destination differs in one structural way. Arm won sockets on power efficiency inside a licensing model that still controls the ISA. RISC-V offers the same efficiency argument plus an open standard a hyperscaler can extend without permission — the property that makes a customizable CUDA-capable head node the socket that could reprice SiFive’s position.

SiFive licenses processor IP for a living, so the SF-2U870 may never book meaningful hardware revenue. What the box sells is schedule compression: every hyperscaler custom-SoC program built on SiFive IP faces a multi-year software phase — OS bring-up, toolchain qualification, workload porting, performance tuning — and BigSky moves that work onto hardware customers can rack today, years before the custom SoC those cores land in tapes out. That bet is funded by the $400 million Series G SiFive raised in April at a $3.65 billion valuation, with NVIDIA among the investors.

The competitive field is not standing still

The challenge is the distance between a porting vehicle and a procurement decision. Production alternatives have shipped at fleet scale for years: Google has migrated 30% of internal applications to Arm-based Axion, Microsoft is scaling Cobalt 200, and AMD and Intel hold the x86 volume that defines server price-performance.

The RISC-V field itself is crowded. Qualcomm’s Dragonfly roadmap pairs Oryon-based C1000 CPUs with the Ventana Micro RISC-V team it acquired in December, and Tenstorrent ships Ascalon-based systems into inference workloads. Alibaba’s XuanTie C950 — a TSMC 5nm, 64-core RISC-V server processor unveiled in March with native AI acceleration — shows the architecture’s momentum on the China side. BigSky’s lead customers are real but unnamed, which keeps the design-win ledger empty for now.

What to watch over the next 12 months: whether a hyperscaler names a custom SoC program built on SiFive datacenter IP; whether Canonical’s native RISC-V builders close the package-testing gap to parity by the 26.10 cycle; whether NVLink Fusion integration with C2C appears in a named SiFive platform; and whether additional RVA23 server silicon reaches public demonstration this year.

For an architecture that spent a decade confined to microcontrollers and niche accelerators, a rackable 2U server that boots two enterprise Linux distros and orchestrates NVIDIA GPU clusters is a genuine inflection point. The software gap that kept RISC-V out of the datacenter is closing on a schedule — and SiFive just moved the clock forward.

Sources