Arke in H1 2027, Astrid by Year-End: Meta Locks In Its Custom-Silicon Escape From Nvidia's Bill

Meta has put dates on its escape route from Nvidia’s invoice. In an interview published September 15, the company said its third-generation custom AI accelerator — MTIA 450, codenamed Arke — will enter data-center production in the first half of 2027, with the fourth generation, MTIA 500 (Astrid), completing design work in about a month and deploying by the end of 2027. Meta expects to use Astrid even more widely than Arke.

The details came from Yee Jiun Song, Meta’s vice president of engineering and the man who runs its custom silicon program, speaking to Bloomberg (syndicated by the Los Angeles Times). They mark the most concrete public timeline yet for the chip line that Meta hopes will bend the cost curve of a compute buildout now measured in gigawatts and roughly $115 billion of planned capital expenditure.

What Meta actually committed to

The headline numbers from the interview:

• MTIA 450 “Arke” — third generation, currently in testing, data-center production in H1 2027. Relative to the MTIA 400, it roughly doubles HBM bandwidth, and it carries specific optimizations for generative-AI inference.
• MTIA 500 “Astrid” — design work completes in roughly a month, deployment by end of 2027, with a broader rollout. It adds about 50% more bandwidth again and up to 80% more HBM capacity over the 450.
• More than a gigawatt committed: measured by energy use, Meta has committed to over 1 GW of these chips over a 12-month period — and “we expect it to accelerate” after that, according to Song, assuming no crash in AI demand.
• Silicon is already back: twelve MTIA 450 chips arrived from TSMC on September 1, and measured performance landed within 2–3% of simulation — the kind of first-silicon accuracy that signals no design snags. On day one, the team ran not only Meta’s own models on them but also models from DeepSeek and Alibaba, suggesting the parts are general-purpose inference workhorses rather than narrow single-model accelerators.
• ~44% total-cost-of-ownership savings versus GPUs on supported workloads — the pitch Meta attaches to the line as part of its capex plan.

Meta designs the chips with Broadcom and manufactures with TSMC. Meta Superintelligence Labs feeds the program early insight into upcoming models and their inference requirements, so the hardware is tuned for workloads that have not shipped yet.

The Olympus cancellation is the real story

The most revealing part of the interview is what Meta chose not to build. The company had planned a chip codenamed Olympus, aimed at both training and inference, slated for 2028 or 2029. It cancelled the project to concentrate on inference — explicitly for cost reasons.

“When you start to build up gigawatts and gigawatts of capacity, you really care about cost,” Song said. A chip that handles both training and inference could be roughly 30% more expensive, and at Meta’s scale that premium becomes “completely unacceptable.”

Read that against the market. Nvidia’s margin lives precisely in selling general-purpose parts that do everything for everybody. Meta’s counter is specialization: a workhorse inference engine with just the memory bandwidth its own ranking, recommendation, and generative workloads need. Song’s claim that the chips beat “whatever Nvidia is currently shipping” on performance per watt and per dollar for Meta’s workloads is credible precisely because the comparison is scoped — these are not frontier training parts, and Meta is not pretending they are. All four generations of the line lean heavily on high-bandwidth memory and deliberately sit out the ultrafast-inference tier.

Why a gigawatt of Arke matters

Context matters for the scale here. Meta accounts for roughly 9% of Nvidia’s revenue, and in February it signed a pact to buy “millions” of Nvidia chips. In July, an internal memo reported by Reuters put Meta’s goal at doubling its computing capacity to 14 GW next year. A gigawatt-plus committed to in-house silicon inside that envelope is not a science project — it is a double-digit percentage of Meta’s fleet designed by Meta, for Meta, with Broadcom collecting design fees instead of Nvidia collecting system margins.

The HBM numbers tell you where the industry’s bottleneck actually is. Every recent custom-silicon effort — Meta’s MTIA line included — is designed around memory: doubling bandwidth generation over generation, stacking 80% more capacity, because memory is what is short, and memory bandwidth is what inference throughput actually depends on at scale. A 44% TCO claim on supported workloads is the arithmetic of a chip that buys exactly the memory it needs and nothing else.

The caveats

Three honest qualifications. First, “committed” is not “deployed” — H1 2027 is a schedule, first silicon is twelve chips, and a few months of trialing and tuning remain while factory production ramps. Second, the TCO savings apply to supported workloads; Meta will keep buying enormous quantities of Nvidia GPUs for training and for latency-critical inference that MTIA explicitly does not target. Third, the whole plan assumes AI demand holds; Song said as much directly.

But the trajectory is unambiguous. After Astrid, Meta says it will push speed and throughput with future generations and lean on fiber-optic interconnect to keep improving. “We have a very robust road map,” Song said. “For the next few years, we expect to continue to build chips that are competitive with what our vendors are building for us.”

For Nvidia, no single gigawatt is existential — but Meta is now the clearest demonstration that the largest GPU buyers intend to be chip designers at scale, one workload class at a time. For everyone else building AI infrastructure, Meta has published the playbook: specialize ruthlessly, cancel what does not pay for itself, and measure everything in cost per watt.