Ask Not for Whom the Fab Bells Toll: Lisa Su Asks AMD's Rivals to Share Taiwan's Packaging Capacity

In the old days of the semiconductor industry, a CEO landing in Taipei meant one thing: a bidding war. You flew in, you sat down with TSMC and its packaging partners, and you tried to outbid your rivals for every spare wafer of capacity, every substrate line, every last SIP ball-mount machine. Lisa Su just landed in Taiwan and did something almost unheard of: she is asking AMD’s competitors to stop bidding against each other — and to share.

What’s happening

AMD’s Chair and CEO is touring Taiwan this week, meeting the island’s advanced-packaging and substrate suppliers, and making an unusual request, according to Startup Fortune: rather than each chipmaker bidding up the price of scarce packaging capacity, the industry should coordinate on advanced-packaging and substrate capacity and share what’s available. The backdrop is a supply squeeze that AMD itself helped create. The company is juggling roughly 14 gigawatts of AI data-center agreements — including 6GW each with OpenAI and Meta, plus Oracle’s commitment to 50,000 MI450 systems. Every one of those gigawatts eventually becomes silicon that has to be packaged, stacked, and shipped.

As part of the trip, AMD has pledged $10 billion through 2029 to its Taiwanese partners — ASE, SPIL, and Unimicron — to lock in packaging and substrate capacity. And Su isn’t stopping in Taiwan: the itinerary reportedly extends to Samsung in South Korea, where the goal is to firm up HBM4 memory supply for next year’s accelerator ramps.

Why packaging is suddenly the bottleneck

For most of the industry’s history, “advanced packaging” was the unglamorous back office of chipmaking — the step where finished dies get mounted, connected, and sealed. The AI era inverted that. Modern accelerators are no longer single chips but systems-in-package: a GPU die from TSMC’s 2nm process, multiple stacks of HBM4 memory perched beside it, and all of it sitting on a giant organic substrate that has to carry thousands of connections without warping.

That means three previously distinct supply chains — leading-edge logic, memory stacking, and substrates — now compete for the same limited pool of packaging equipment and engineers. CoWoS-style wafer-level packaging, 12-high HBM4 stacks, and large-body substrates are each capacity-constrained in their own right. When OpenAI signs a 6GW deal and Meta follows with another 6GW, the constraint isn’t the number of GPU dies AMD can design — it’s whether ASE has a free line to bond them and whether Unimicron can deliver substrates fast enough.

AMD’s Helios rack-scale systems, which entered mass production this summer with Samsung as HBM4 supplier and ASE handling packaging, made the dependency explicit. The MI450 generation pairs a 2nm logic die with Samsung’s 12-high HBM4 (24GB to 36GB stacks) — a combination that eats packaging capacity at a rate the island has never seen.

The 14GW problem

The scale of AMD’s commitments explains the urgency. The OpenAI partnership alone — first announced in October 2025 and expanded since — calls for 6 gigawatts of Instinct GPUs, with the first 1GW of MI450 deployments ramping in the second half of 2026. Meta followed in February with its own 6GW commitment, co-engineering a custom MI450 variant for its workloads, again with first shipments in 2H 2026. Add Oracle’s 50,000-MI450 order and other deals, and AMD is sitting on roughly 14GW of demand it must convert into delivered silicon.

That’s a nice problem to have, but only if the supply chain can actually deliver it. AMD’s data-center revenue hit a record $5.8 billion in Q1 2026, up 57% year over year, and the company guided to $11.2 billion for Q2. Analysts at Futurum noted that at Advancing AI 2026 in July, Su claimed “the world’s best AI rack” and raised AMD’s total addressable market estimate to $2 trillion by 2030. All of that rests on packaging capacity that is, today, a shared and contested resource.

Unusual diplomacy, unusual times

The most striking part of the story is the ask itself. Chipmakers coordinating capacity with suppliers is normal; chipmakers asking their direct competitors to hold hands at the packaging line is not. In a market where AMD, Nvidia, and every AI ASIC hopeful are all chasing the same CoWoS lines and HBM stacks, capacity sharing sounds almost cartel-like — or, read more charitably, like an acknowledgment that the AI buildout has outgrown the zero-sum game.

There’s precedent for the softer version of this. TSMC has historically allocated scarce capacity by customer tier and long-term commitment rather than pure auction. Samsung’s HBM4 deal with AMD, described in March as a sole-supply arrangement for Helios, shows how deep the bilateral commitments now run. What’s new is a CEO explicitly pitching cross-rival coordination as the fix — effectively arguing that if everyone bids capacity up, everyone’s AI roadmaps slip together, so nobody should bid at all.

Whether rivals listen is another matter. Nvidia’s own Taiwan commitments run deep, and every AI chip hopeful — from Broadcom’s custom accelerators to the Etched inference startups of the world — needs the same substrates and packaging lines. Su’s $10 billion pledge buys AMD priority with ASE, SPIL, and Unimicron; it doesn’t buy Nvidia’s cooperation.

What to watch

Three signals will tell us whether this diplomacy works. First, whether packaging giants like ASE publicly acknowledge any coordination framework at their upcoming earnings calls. Second, whether AMD’s 2H 2026 MI450 ramps for OpenAI and Meta actually hit their first-gigawatt milestones on schedule — the clearest proof that capacity is flowing. Third, what comes out of Su’s Samsung visit: HBM4 supply for 2027 is the other half of the squeeze, and Economic Times reports AMD plans to “substantially increase supply in 2027,” which requires memory locked in now.

The compute arms race is usually told as a story of architectures and benchmarks. Lisa Su’s Taiwan tour is a reminder that in 2026, it’s equally a story of substrates, stack-bonding machines, and the polite fiction that rivals in a $30-trillion buildout can share a factory line. The fab bells toll for everyone — the question is whether the industry rings them together.