IBM's Dual-ISA Mainframe Chip Runs Arm and z/Architecture in the Same Cores

At this year’s Hot Chips symposium at Stanford, IBM announced something the industry hasn’t seen in roughly three decades: a production-track dual-ISA processor. The company’s next-generation mainframe chip for IBM Z and LinuxONE systems is built so that every single core can natively execute both z/Architecture and Arm AArch64 instructions — not through binary translation, not through separate Arm and Z cores bolted onto one die, but in the same out-of-order core, switching between ISAs in nanoseconds.

It is the first processor milestone from the IBM–Arm collaboration established in April 2026, and it is a genuinely strange piece of engineering in the best sense. The last serious attempt at a dual-ISA chip was IBM’s own PowerPC 615 in the mid-1990s, which could execute PowerPC and x86 instructions and was a commercial failure. Thirty years later, IBM is trying again — this time with the mainframe as the prize.

What IBM actually announced

The headline specifications, from IBM’s announcement and the Hot Chips session:

• 2nm process node, with 11 high-performance cores operating at more than 5.7 GHz
• Each core implements both z/Architecture and AArch64 natively — a little-endian Arm implementation alongside big-endian z/Architecture, with AArch64 v9.3 including SVE and SVE2 support
• 2,792 implemented AArch64 instructions — more than twice the count of the Z instruction set, prompting IBM’s presenters to joke about the word “reduced” in RISC
• Large cache hierarchy retained from the Z lineage: 36MB private L2 per core joined into a 432MB virtual L3 and 3.5GB virtual L4
• A dedicated on-chip DPU for I/O acceleration, plus dedicated silicon blocks for AI, compression, cryptography, and sort
• AI inference accelerators aimed at in-transaction fraud detection
• SMT=2 design, with the platform scaling to hundreds of cores and tens of terabytes of memory at the system level

Crucially, IBM claims Arm SystemReady compliance, meaning off-the-shelf Arm software sees a standard, native Arm platform. Arm Linux distributions run unmodified. IBM detailed how the existing Z core machinery was extended rather than replaced: automation consumes Arm’s XML architecture descriptions to feed the decoders, dispatch and issue repurpose register rename for the GR16–31 range, and even classic CISC machinery like memory copy-and-clear gets reused for Arm code paths.

The Z platform’s reliability features carry over untouched — 99.999999% availability targets, error checking across arrays and dataflows, transparent recovery from transient faults, core sparing for persistent faults, concurrent repair, and RAIM memory protection. This is what distinguishes the chip from a general-purpose server part: it inherits sixty years of mainframe engineering while opening a door to the Arm ecosystem.

The AI accelerator alongside it

IBM also presented a second-generation on-chip AI inference accelerator built for larger enterprise inference workloads. The part packs 16 active AI cores plus one redundant spare — fault-tolerant AI silicon, in keeping with mainframe philosophy — supporting FP4 and MXFP4 data types with up to 4x the TOPS of the previous generation. It attaches 96GB of HBM3e running at roughly 4TB/s, about 20x the memory bandwidth of the current generation, connected via PCIe Gen6 as a low-latency peer-to-peer interface. Security spans confidential computing with data and model protection at rest, in transit, and in use, including quantum-safe cryptography.

The pairing is deliberate: in-transaction AI — fraud detection on a payment rail, risk scoring inside a trade — is the workload where mainframes still own the ground truth, and it increasingly demands inference capacity that a CPU alone can’t supply.

Why this matters

IBM says roughly 70% of the world’s transaction volume still flows over Z mainframes, concentrated in banking, payments, insurance, telecom, and government — regulated industries where uptime is measured in seconds per century. But the software gravity of the industry has shifted: with more than 22 million developers, the Arm ecosystem is where cloud-native and AI software is being built first, from Kubernetes operators to inference stacks.

Until now, Z shops faced an unattractive choice. They could keep mission-critical transaction systems on z/OS and watch the modern software ecosystem drift away, or they could migrate workloads to x86 or Arm clouds and give up the mainframe’s reliability, encryption, and audit posture. The dual-ISA chip dissolves that trade-off: organizations can run Arm-native Linux environments simultaneously with z/OS and Linux on IBM Z in the same logical partitions, orchestrated through Linux KVM and OpenShift Virtualization, with the Z accelerators (crypto, GZIP compression, the AI unit) exposed as standard platform devices to Arm Linux with comparable latency to native Z instructions.

For Arm, the win is equally clear. “As AI scales, more of the computing landscape is converging on Arm,” said Mohamed Awad, EVP of Cloud AI at Arm. Landing native Arm execution inside the most mission-critical enterprise platforms extends Arm’s momentum from phones and cloud servers into territory it has never touched.

The bigger picture

The announcement lands amid a Hot Chips program themed around agentic computing, where every major player — Intel with Diamond Rapids, Nvidia with Vera Rubin, Meta with MTIA 300’s in-package networking, AMD, Google, and Microsoft with their accelerator roadmaps — is converging on the same conclusion: the next era of AI infrastructure demands co-design of compute, memory, interconnect, and software.

IBM’s answer is contrarian but coherent. Rather than chasing GPU-scale training, it is defending the transaction-processing franchise and bolting the entire Arm software universe onto it — betting that regulated enterprises will want AI and cloud-native workloads running next to the systems of record, under mainframe-grade reliability, rather than in a separate cloud. The dual-ISA core may even prove to be the fastest Arm core in existence once independent benchmarks arrive, given that enormous cache hierarchy.

The caveats are real: IBM’s own release notes the design represents “goals and objectives only,” silicon isn’t expected until a future Z generation, and the PowerPC 615 is a reminder that dual-ISA chips have failed before. But as a statement of direction, it is one of the boldest architecture moves of the year — the mainframe refusing to become a museum piece, and instead trying to become the one machine that runs everything.

Sources

Primary coverage and technical detail from IBM’s announcement, ServeTheHome’s live session notes, VentureBeat, WCCFTech, and HPCwire — see the sources list for this post.