11.95 Nanometers Without EUV: CXMT's G5 DRAM Node Enters Mass Production

In the physics of DRAM scaling, the half-pitch is the honest number. Marketing nodes — “1c,” “1γ,” “12nm-class” — are shorthand; the half-pitch of the memory array is what a fab can actually print. On Sunday, at the 2026 World Manufacturing Convention in Hefei, China’s ChangXin Memory Technologies (CXMT) announced that its fifth-generation DRAM platform, G5, has entered mass production with an active-area half-pitch of 11.95 nanometers — a figure that puts the Chinese memory maker’s volume output in the same league as the most advanced DRAM being shipped by Samsung, SK Hynix, and Micron.

And it did so without a single EUV lithography machine.

What CXMT Announced

The G5 platform announcement, delivered in CXMT’s hometown convention hall and confirmed in a company statement to the Global Times, carries four hard numbers:

• 11.95nm memory-array half-pitch, achieved with self-aligned quadruple patterning (SAQP) — the multiply-and-etch technique that lets DUV immersion scanners print features far below their nominal resolution.
• 45:1 capacitor aspect ratio, enabled by process-flow redesign and new material integration. DRAM capacitors are the deepest structures in volume semiconductor manufacturing; a taller, narrower stack at a finer pitch is the core of density scaling.
• DRAM-optimized HKMG (high-k metal gate) process, cutting the core cell array height to 6,762 nanometers — a flatter array that eases etch and fill uniformity across the wafer.
• At least 50% more dies per wafer versus the fourth-generation platform, alongside improvements in energy efficiency and cost.

Alongside the platform, CXMT said two LPDDR5X products built on G5 have entered mass production: both 24Gb (3GB) devices — 50% higher capacity than comparable prior-generation parts — in 496-ball and 245-ball packages, aimed at mid- to high-end smartphones and portable consumer electronics, and already integrated into mainstream flagship Chinese smartphones.

The company also reported progress in key process modules including interface engineering, saddle-fin structures, and low-k spacer bitlines — the unglamorous process work that determines whether a node scales in PowerPoint or in a fab.

Why SAQP Instead of EUV Is the Real Story

Since 2019, U.S. export controls have barred Chinese chipmakers from buying ASML’s EUV scanners. Samsung, SK Hynix, and Micron all use EUV for their leading-edge DRAM nodes. The received wisdom — repeated for years in industry analysis — was that this denial would cap Chinese memory at a generation or two behind, indefinitely.

CXMT’s answer has been to industrialize multipatterning. SAQP sequences four or more deposition and etch steps to subdivide what a DUV scanner prints once, at the cost of enormous process-control burden: every added pattern transfer compounds overlay error and defects. Reaching 11.95nm half-pitch in volume production — with die yield per wafer up more than 50% over the previous node — is the strongest evidence yet that the DUV ceiling is higher than assumed, at least for the periodic, highly regular structures that DRAM arrays favor.

There are caveats. DRAM’s regular geometries are more multipatterning-friendly than logic’s irregular wiring, which is why SMIC’s comparable logic achievements remain a node behind. And half-pitch parity does not mean parity in everything: bit density per die, interface speeds, HBM integration, and yields at 24Gb capacities are all dimensions where the Korean and American leaders still hold real leads — as CXMT’s own LPDDR6 debut showed, its first-generation speeds trail SK Hynix’s EUV-based parts by a measurable margin.

But the direction of travel is unambiguous. In February 2025, CXMT was reported producing DDR5 on a 17nm-class node. Nineteen months later it is in mass production at 11.95nm with density economics that approach the leaders’ volume platforms. That is a compression of the technology gap from roughly two generations to something closer to one — and, on the specific metric of array scaling, to near-zero.

The Market It Lands In

The timing could hardly matter more. TrendForce reported that global DRAM industry revenue jumped 59.5% quarter-on-quarter in Q2 2026 to roughly $154.7 billion, as AI server demand for HBM3E and RDIMMs pushed contract prices up faster than supply could respond. Supply expansion “continues to lag demand growth” — the textbook condition under which a new entrant with credible volume is welcome rather than disruptive.

Within that boom, the shares tell the competitive story. Samsung led Q2 with about 38% of the DRAM market, SK Hynix held 25%, Micron 24% — and CXMT’s share rose to approximately 10%, making it firmly the world’s No. 4 producer. Bloomberg reported in August that CXMT was narrowing the gap in smartphone memory specifically; its LPDDR6 entered mass production ahead of Samsung and SK Hynix’s next-gen mobile parts and debuted in Xiaomi’s 18 Fold flagship. Sunday’s G5 announcement supplies the process foundation under that product momentum: LPDDR6 and whatever follows will ride on this node.

Two demand-side forces amplify the strategic weight. First, on-device AI: local models, real-time translation, and agentic assistants hit memory-bandwidth walls before they hit compute walls, which is why every Chinese flagship SoC this cycle — Xiaomi’s 3nm Xring O3 included — was designed around next-generation memory. A domestic LPDDR supply at frontier density is now a national AI-infrastructure priority, not a procurement preference. Second, memory-hungry AI datacenters have squeezed mobile makers out of allocation queues entirely: LPDDR5X spot prices rose nearly 80% in a single quarter earlier this year, giving every OEM reason to qualify a second source. CXMT says its G5 parts are already in mainstream Chinese flagship phones.

The Geopolitical Overlay

None of this happens in a commercial vacuum. CXMT is on the U.S. Department of Defense’s “Chinese military-industrial complex companies” list — a designation it is actively challenging in court — and its rise is a standing argument in Washington over whether export controls slow leading-edge competitors or simply redirect their innovation into patterning workarounds. The company’s CEO has publicly said CXMT remains open to supplying Apple, an idea that surfaces periodically and faces obvious political resistance.

For Beijing, the math is straightforward. DRAM is among the most concentrated markets in technology: three foreign firms control roughly 90% of global supply, and every Chinese AI datacenter, phone, and server buys from that oligopoly. A domestic supplier at 10% share with volume-production parity on node scaling converts a strategic vulnerability into a bargaining position — precisely the “supply-chain resilience and more sourcing options” framing that analyst Ma Jihua gave the Global Times at the announcement.

For Samsung, SK Hynix, and Micron, the comfortable reading is that CXMT remains a fast follower: behind on HBM (where CXMT has only begun domestic HBM3E work), behind on interface speeds, dependent on DUV with its inherent cost-per-layer penalty. The uncomfortable reading is the yield curve. DDR5 yields above 90% on the prior node, 50%+ die-per-wafer gains on G5, LPDDR6 first-to-handset — each datapoint narrows the room for complacency. The DRAM industry has seen a fast follower catch up before; its name was Samsung, and the incumbents it displaced were American.

What to Watch

Three markers will show whether G5 is a milestone or a plateau. First, 24Gb yield data in the field — G5’s density claims will be tested by how many working gigabit-die each wafer really yields at mature volumes, numbers only teardowns and supply-chain data will reveal. Second, whether LPDDR6 speeds climb on the G5 node toward SK Hynix’s EUV-class 14.4 Gbps, closing the interface gap that is currently the most visible DUV penalty. Third, HBM: if CXMT can stack G5 die into competitive HBM3E-class products for the domestic accelerator market, the significance jumps from mobile memory to the AI compute chain itself.

One number from Hefei is worth holding onto regardless: 11.95nm, in mass production, on equipment export controls were specifically designed to deny. The controls didn’t fail — they forced a harder, slower road. But the road, it turns out, goes where the destination is anyway.